1) Field of the Invention
The present invention relates to an undercoating material used preferably for forming wiring on a semiconductor substrate, a filler material and a wiring formation method using the same. The undercoating material referred to herein indicates (a) an undercoating layer which is formed on a substrate before formation of a photoresist layer on the substrate whereby a reflected exposure light from the surface of the substrate at the time of patterning of a photoresist is prevented from entering the photoresist, to achieve improvement in the resolution of the photoresist pattern, (b) an undercoating layer suitable for a silicon bilayer resist, which is characterized by improving the patterning accuracy of a resist by constituting a photoresist layer used in lithography for wiring, from two layers, that is, an undercoating layer including an organic film and a silicon-containing upper resist layer, and (c) an undercoating layer suitable for multilayer process, which improves the patterning accuracy of a resist by constituting a photoresist layer used in lithography for wiring, from a multilayer structure including at least an undercoating layer including an organic film, an intermediate layer, and an upper photoresist layer. The filler material referred to herein indicates (d) a material for filling an etching space for forming a dual damascene structure composed at least of a first etching space formed in a low-dielectric layer on a substrate and a second etching space communicating with the first etching space and different in shape and dimension to those of the first etching space.
2) Description of the Related Art
As is well-known, a semiconductor substrate includes a dielectric layer (insulating layer) laminated on a substrate such as silicon wafer, wherein a semiconductor wiring structure is constituted by forming a patterned conductive layer (wiring layer) in the dielectric layer on the semiconductor substrate.
For formation of the wiring structure, two methods are mainly used. The first method involves forming a conductive layer uniformly on the dielectric layer, then forming a photoresist on the conductive layer, irradiating (light-exposing) the photoresist with a pattern light and develop it to form a resist pattern, patterning the conductive layer by etching using the resist pattern as a mask to form a wiring layer, removing the resist pattern and laminating a dielectric layer thereon thereby constituting a wiring layer in the dielectric layer.
The second method involves forming a photoresist pattern on the dielectric layer, then forming a wiring groove (trench) in the dielectric layer by etching using the resist pattern as the mask, removing the resist pattern, embedding a conductive material in the wiring groove and laminating a dielectric layer thereon thereby forming a semiconductor wiring structure.
When the wiring structure is multi-layered, the step of forming a wiring layer in each method is repeatedly carried out to laminate a plurality of wiring layers, and a step of forming a via wire is necessary between the steps of forming wiring layers. The step of forming the via wire is a step which involves forming a via hole in a dielectric layer serving as an interlaminar insulating layer between lower and upper wiring layers, and depositing a conductive material into the via hole by a gaseous phase process or embedding a conductive material therein thereby forming a via wire connecting the lower wiring layer electrically to the upper wiring layer.
In either of the two wiring methods, there arises the phenomenon that upon patterning by exposing the photosensitive layer to light, the exposure light penetrates the resist layer, the penetrating light is reflected by the surface of the undercoating layer, and the reflected light enters a portion which should not be exposed to light. Such an entrance of the reflected light into the photoresist layer results in deterioration of the patterning resolution of the photoresist. In the conventional method, therefore, a resin composition containing a material absorbing exposure light is applied onto a semiconductor substrate to form an undercoating layer before formation of a photoresist layer on the substrate, and then a photoresist layer is formed on the undercoating layer. The undercoating layer is also referred to as an anti reflective coating film from the viewpoint of its action.
As the material of the anti reflective coating film, various materials have been proposed. For example, a resin composition including a polymer having an iminosulfonate group and a solvent is proposed as described in Japanese Patent Application Laid-open No. H10-319601.
As described in Japanese Patent Application Laid-open No. 2000-512336, a light-absorbing polymer including a polymer having a hydroxystyrene unit that has a specific substituent group including a sulfonate is developed, and as described in Japanese Patent Application Laid-Open No. 2000-512402, an anti reflective coating film material including the light absorbing polymer and a solvent is proposed.
In addition to the major property of anti-reflection, the undercoating layer for preventing reflection of exposure light is required to be removable by any method after the etching treatment of the lower conductive layer or the dielectric layer using the photoresist pattern as the mask.
Discussing the conventional undercoating layer from the viewpoint of removal of the undercoating layer after used as an anti reflective coating film, the anti reflective coating film material disclosed in the Japanese Patent Application Laid-open No. H10-319601 uses a polymer having an iminosulfonate group as a resin component, and the resin component is insoluble in a stripping solution for photoresist. In the techniques disclosed in the Japanese Patent Application Laid-open No. H10-319601, therefore, an upper photoresist pattern is removed with the stripping solution, and then the remaining undercoating layer is removed by O2 plasma ashing.
The resin components disclosed in the Japanese Patent Application Laid-open Nos. 2000-512336 and 2000-512402 are also insoluble in the stripping solution for photoresist so that after a photoresist pattern is removed with the stripping solution, the remaining undercoating layer is removed by O2 plasma ashing.
As is well known, in the semiconductor wiring structure, a dielectric layer with which wiring layers are covered and thereby electrically separated from other wiring layers is required to have a dielectric constant as low as possible so as not to influence the electric characteristics of the wiring layers. Specifically, the dielectric constant (k) of the dielectric material is as low as 3.0 or less in majority of cases. However, a material having such low dielectric constant is poor in resistance to O2 plasma ashing so that by exposure to O2 plasma, its surface is easily deteriorated, or the dielectric constant is increased.
When the conventional anti reflective coating film is formed on a semiconductor substrate having the dielectric layer of such low dielectric constant, O2 plasma ashing for removing the anti reflective coating layer may cause deterioration such as corrosion of the dielectric layer or rise in the electric constant, and as a result, there arises a problem that the electric characteristics of the wiring layer are adversely affected.
In production of the semiconductor wiring structure, the patterning of the photoresist and the undercoating layer by lithography is carried out for forming the wiring layer on the semiconductor by etching or for forming the wiring groove for embedding the wiring layer, as described above. The regulatory factor in the lithographic step includes many factors such as regulation of current intensity and voltage in a stepper for generating exposure light, adjustment of a focal point of a lens, accuracy of a photomask, accuracy of an attachment position, and coating properties and curing characteristics of a photoresist composition. When these regulatory factors vary for some reason, there occurs patterning insufficiency, due to which the lithographic step has to be conducted again. In this case, disposal of the semiconductor substrate and use of a new semiconductor substrate lead to waste of resources and exert an adverse effect on the environment. In the production process, it is thus required to recover the semiconductor substrate by removing the photoresist layer and undercoating layer that have been subjected to insufficient lithography. Removal of the undercoating layer in a recovering step for re-generating the semiconductor substrate is referred to as rework treatment, which is an important process in terms of economical efficiency in the production of the semiconductor wiring structure. Discussing the conventional anti reflective coating film from the viewpoint of such rework treatment, the conventional anti reflective coating layer is not suitable because there is a problem that it should be removed by O2 plasma ashing easily causing deterioration in the characteristics of a semiconductor substrate after rework treatment.
On the other hand, high integration is an everlasting task for a device having the wiring structure described above, and there is demand for finer wiring. For achieving finer wiring, it is necessary to improve the patterning resolution of the photoresist for lithography and to improve the patterning resolution of the wiring layer or the wiring groove formed by etching using a resist-pattern as the mask that has been obtained by exposure. As the thickness of the resist layer becomes thinner, the accuracy of pattern transfer to the resist using the exposure device and the wiring pattern mask can be improved. On the other hand, such a thin resist layer results in difficulty in maintaining the resistance of the resist layer in the step of etching the undercoating layer using the resist pattern as the mask, and disadvantageous effect in the etching resolution of the wiring layer or the wiring groove. To improve resist resistance, thicker layer is preferable. Therefore, there is an antinomic requirement in the determination of the photoresist thickness for improving the accuracy of lithography with a photoresist. As a technique for solving the problem to improve the accuracy of lithography with the photoresist, there is provided a wire formation method using a silicon bilayer resist and a wire formation method using a multilayer resist (Japanese Patent Application Laid-open No. H10-92740).
The former wire formation method is a lithographic technique for improving pattern transfer accuracy in spite of a thick resist layer by forming a resist not into a monolayer structure but into a two-layer structure. In this technique, a thick undercoating layer consisting of an organic polymer material is formed on a substrate, and an upper thin resist layer consisting of a silicon-containing photoresist material highly resistant to oxygen plasma etching is formed thereon. Thereafter, a wiring pattern is transferred to the upper resist layer to form an upper resist pattern. The undercoating layer is then patterned by oxygen plasma etching using the resulting upper resist pattern as a mask. The resist layer thus obtained is a layer that is thick as a whole with high pattern transfer accuracy.
Materials for constituting the silicon bilayer resist are, for example, disclosed in Japanese Patent Application Laid-open No. 2002-033257. In this application, the undercoating layer is referred to as a first resist layer, and the upper resist layer is called a second resist layer.
It is described therein that, as a general material constituting the first resist layer, a condensed polymer compound such as novolak resin, phenol resin and cresol resin and a vinyl polymer having an aromatic ring such as a phenyl group or a condensed aromatic ring such as naphthyl group or anthryl group in its side chain is used, and that various kinds of known photoresists can also be preferably used.
It is described therein that, as the silicon-containing photosensitive composition used in the second resist layer, a known one can be used.
In the silicon bilayer resist process, it is necessary to remove the resist by any method after finishing etching of the deeper conductive layer or dielectric layer using the resist pattern as the mask. In Japanese Patent Application Laid-open No. 2002-033257, a silicon-containing upper resist layer is removed by wet stripping treatment unique to this patent application, and the remaining undercoating layer is removed by O2 plasma ashing.
It is well-known that in the semiconductor wiring structure, a dielectric layer with which wiring layers are covered and thereby electrically separated from other wiring layers is required to have a dielectric constant as low as possible so as not to influence the electric characteristics of the wiring layers. Specifically, the dielectric constant (k) of the dielectric material is as low as 3.0 or less in majority of cases. However, a material having such low dielectric constant is poor in resistance to O2 plasma ashing so that by exposure to O2 plasma, its surface is easily deteriorated, or the dielectric constant is increased.
When a resist pattern made of the conventional silicon bilayer resist is formed on a semiconductor substrate having the dielectric layer of such low dielectric constant to form a wiring layer, O2 plasma ashing for removing the undercoating layer on the substrate may cause deterioration such as corrosion of the dielectric layer or rise in the electric constant, and as a result, there arises a problem that the electric characteristics of the wiring layer are adversely affected.
In production of the semiconductor wiring structure, the patterning of the photoresist and the undercoating layer by lithography is carried out for forming the wiring layer on the semiconductor by etching or for forming the wiring groove for embedding the wiring layer, as described above. The regulatory factor in the lithographic step includes many factors such as regulation of current intensity and voltage in a stepper for generating exposure light, adjustment of a focal point of a lens, accuracy of a photomask, accuracy of an attachment position, and coating properties and curing characteristics of a photoresist composition. When these regulatory factors vary for some reason, there occurs patterning insufficiency, due to which the lithographic step has to be conducted again. In this case, disposal of the semiconductor substrate and use of a new semiconductor substrate lead to waste of resources and exert an adverse effect on the environment. In this production process, it is thus required to recover the semiconductor substrate by removing the photoresist layer and undercoating layer that have been subjected to insufficient lithography. Removal of the undercoating layer in the recovering step for re-generating the semiconductor substrate is referred to as rework treatment, which is an important process in terms of economical efficiency in the production of the semiconductor wiring structure. Discussing the conventional undercoating layer from the viewpoint of such rework treatment, the conventional undercoating layer is not suitable because there is a problem that it should be removed by O2 plasma ashing easily causing deterioration in the characteristics of a semiconductor substrate after rework treatment.
As the technique of making a photoresist layer into a substantially two-layer structure, a technique of arranging, below the resist layer, an undercoating layer for the purpose of preventing exposure light from being reflected is known besides the technique of using the silicon bilayer resist. The undercoating layer is composed of a resin composition having a high ability to absorb the exposure light, and plays a role in preventing reflection of exposure light by absorbing patterning light for the upper resist thereby preventing the light from reaching the surface of the substrate. It may be considered that the material for forming the undercoating layer can also be used to form an undercoating layer in the silicon bilayer resist. If the anti reflective coating film can be removed without using O2 plasma ashing, the problem in the wiring formation method using the silicon bilayer resist can be solved.
As a material for the ant reflective coating film, various compositions have been proposed. For example, a resin composition containing a polymer having an iminosulfonate group and a solvent is proposed (Japanese Patent Application Laid-open No. H10-319601).
A light-absorbing polymer containing a polymer having a hydroxystyrene unit that has a specific substituent group containing a sulfonate has been developed, (Japanese Patent Application Laid-open No. 2000-512336) and a anti reflective coating film material including the light absorbing polymer and a solvent has been proposed (Japanese Patent Application Laid-open No. 2000-512402).
The anti reflective coating film material disclosed in the Japanese Patent Application Laid-open No. H10-319601 uses a polymer having an iminosulfonate group as a resin component, and the resin component is insoluble in a stripping solution for photoresist. In the techniques disclosed in the Japanese Patent Application Laid-open No. H10-319601, therefore, the upper photoresist pattern is removed with the stripping solution, and then the remaining undercoating layer is removed by O2 plasma ashing.
The resin components disclosed in the Japanese Patent Application Laid-open Nos. 2000-512336 and 2000-512402 are also insoluble in the stripping solution for photoresist, and after the photoresist pattern is removed with the stripping solution, the remaining undercoating layer is removed by O2 plasma ashing.
Accordingly, even if the conventional anti reflective coating film is employed as the undercoating layer in the silicon bilayer resist, the problem attributable to removal of the undercoating layer cannot be solved.
The latter of the aforementioned wiring formation methods (Japanese Patent Application Laid-open No. H10-92740) or the multilayer process is the technique of forming the resist not into the single layer but into the multilayer structure, whereby (1) the uppermost photoresist layer to which the pattern is first transferred through the mask is made thin to improve both resolution and focal depth in lithography and (2) the anti reflective coating film etc. having less film interfering effect and high resistance to etching is formed as a multilayer below the uppermost layer, to give a resist pattern excellent in dry etching resistance with high pattern transfer accuracy. In this technique, a composite anti reflective coating film is first formed on a substrate. This composite anti reflective coating film is a multilayer composed for example of a carbon film and a silicon oxide film and if necessary a silicon nitride barrier layer therebetween. An upper thin photoresist layer is formed on the multilayer. Thereafter, a wiring pattern is transferred by lithography to the upper photoresist layer, to form an upper resist pattern. The silicon oxide film as an intermediate layer is then subjected to etching with the resulting upper resist pattern as the mask to transfer the pattern. Subsequently, the carbon film as an undercoating layer is subjected to etching using the upper resist pattern and the intermediate layer pattern as the mask, to transfer the wiring pattern. Finally, the upper resist pattern and the intermediate layer pattern are removed, whereby a carbon film (undercoating layer) pattern excellent in dry etching resistance with high pattern transfer accuracy is obtained. The substrate is etched according to the pattern with the undercoating layer pattern as the mask.
In the multilayer resist, it is necessary to remove the finally remaining undercoating layer (carbon film) pattern by any method after finishing patterning by etching processing of the lower conductive layer or dielectric layer. In Japanese Patent Application Laid-open No. H10-92740, the pattern is removed by O2 plasma ashing.
It is well-known that in the semiconductor wiring structure, a dielectric layer with which wiring layers are covered and thereby electrically separated from other wiring layers is required to have a dielectric constant as low as possible so as not to influence the electric characteristics of the wiring layers. Specifically, the dielectric constant (k) of the dielectric material is required to be as low as 3.0 or less. However, a material having such low dielectric constant is poor in resistance to O2 plasma ashing so that by exposure to O2 plasma, its surface is easily deteriorated, or the dielectric constant is increased.
When a resist pattern made of the conventional multilayer resist is formed on a semiconductor substrate having the dielectric layer of such low dielectric constant to form a wiring layer, O2 plasma ashing for removing the undercoating layer on the substrate may cause deterioration such as corrosion of the dielectric layer or rise in the electric constant, and as a result, there arises a problem that the electric characteristics of the wiring layer are adversely affected.
In production of the semiconductor wiring structure, the patterning of the photoresist and the undercoating layer by lithography is carried out for forming the wiring layer on the semiconductor by etching or for forming the wiring groove for embedding the wiring layer, as described above. The regulatory factor in the lithographic step includes many factors such as regulation of current intensity and voltage in a stepper for generating exposure light, adjustment of a focal point of a lens, accuracy of a photomask, accuracy of an attachment position, and coating properties and curing characteristics of a photoresist composition. When these regulatory factors are varied for some reason, there occurs patterning insufficiency, due to which the lithographic step has to be conducted again. In this case, disposal of the semiconductor substrate and use of a new semiconductor substrate lead to waste of resources, and exert an adverse effect on the environment. When insufficiency in lithography is found out in such a production process, it is therefore necessary to recover the semiconductor substrate by removing the resist remaining on the substrate. Removal of the defective resist in the recovering step for re-generating the semiconductor substrate is referred to as rework treatment, which is an important process in terms of economical efficiency in the production of the semiconductor wiring structure. Discussing the conventional undercoating layer from the viewpoint of such rework treatment, the conventional undercoating layer is not suitable because there is a problem that it should be removed by O2 plasma ashing easily causing deterioration in the characteristics of a semiconductor substrate after rework treatment.
A phenomenon called poisoning that often occurs upon use of a low-dielectric layer as an interlaminar insulating layer for supporting the wiring layer is recently problematic in the step of forming a resist pattern, and there is a need for solving it.
The poisoning phenomenon occurs easily upon use of the low-dielectric layer as the interlaminar insulating layer, and cannot be prevented by the conventional undercoating material. Accordingly, there is demand at present for development of an undercoating material capable of maintaining easiness of removal after use and of preventing the poisoning phenomenon in the wiring structure forming process using the low-dielectric layer.
As the technique of making a photoresist layer into a substantially multilayer (two-layer) structure, a technique of arranging, below the resist layer, an undercoating layer for the purpose of preventing exposure light from being reflected is known besides the technique of using the multilayer resist. The undercoating layer is composed of a resin composition having a high ability to absorb the exposure light, and plays a role in preventing reflection of exposure light by absorbing patterning light for the upper resist thereby preventing the light from reaching the surface of the substrate. If the anti reflective coating film can be removed without using O2 plasma ashing, and can prevent the adverse influence of poisoning on the resist layer, the problem in the wiring formation method using the multilayer resist can be solved.
As a material for the anti reflective coating film, various materials have been proposed. For example, a resin composition containing a polymer having an iminosulfonate group and a solvent is proposed. (Japanese Patent Application Laid-open No. H10-319601)
A light-absorbing polymer containing a polymer having a hydroxystyrene unit that has a specific substituent group containing a sulfonate has been developed, (Japanese Patent Application Laid-open No. H2000-512336) and an anti reflective coating film material including the light absorbing polymer and a solvent has been proposed. (Japanese Patent Application Laid-open No. H2000-512402)
The anti reflective coating film material disclosed in the Japanese Patent Application Laid-open No. H10-319601 uses a polymer having an iminosulfonate group as a resin component, and the resin component is insoluble in a stripping solution for photoresist. In the techniques disclosed in the Japanese Patent Application Laid-open No. H10-319601, therefore, the upper photoresist pattern is removed with the stripping solution, and then the remaining undercoating layer is removed by O2 plasma ashing.
The resin components disclosed in the Japanese Patent Application Laid-open Nos. 2000-512336 and 2000-512402 are also insoluble in the stripping solution for photoresist so that after the photoresist pattern is removed with the stripping solution, the remaining undercoating layer is removed by O2 plasma ashing.
Accordingly, even if the conventional anti-reflective coating film is employed as the undercoating layer in the multilayer resist, the problem attributable to removal of the undercoating layer cannot be solved.
In light of a fundamental wiring structure in a semiconductor integrated circuit, it is well-known that the fundamental wiring structure is a structure wherein a lower wiring layer formed directly or indirectly on a semiconductor substrate and an upper wiring layer formed via an interlaminar insulating layer on the lower wiring layer are connected through a via wire formed so as to penetrate the interlaminar insulating layer. By combining a plurality of such wiring structures, the multilayer wiring structure of a semiconductor integrated circuit is formed.
As a method of realizing the multilayer wiring structure by using copper excellent in electro-migration resistance, a dual damascene process is known. In the dual damascene process, a dual damascene structure composed at least of a first etching space formed in a low-dielectric layer on a substrate and a second etching space communicating with the first etching space and different in shape and dimension to those of the first etching space is formed. The above-described wiring structure is realized by embedding a conductive material in the dual damascene structure.
The fundamental dual damascene process is described in more detail by reference to FIGS. 1A to 1D and FIGS. 2E to 2H.
As illustrated in FIG. 1A, an interlaminar insulating layer 2 is formed on substrate 1. SiO2, carbon doped oxide (SiON), spin-on-glass (hereinafter, “SOG”) or the like are used as a material for forming the interlaminar insulating layer 2. A resist layer 3 is formed and patterned on the interlaminar insulating layer 2. The interlaminar insulating layer 2 is etched selectively with the patterned resist layer 3 as the mask, and then the resist layer 3 is removed, whereby a wiring groove (trench) 4 is formed as illustrated in FIG. 1B. A barrier metal 5 is then deposited on the surface of the interlaminar insulating layer 2 having the wiring groove 4 formed therein as described above, whereby the adhesion between copper to be embedded in the wiring groove 4 and the interlaminar insulating layer 2 is improved while a barrier metal film for preventing diffusion of copper into the interlaminar insulating layer 2 is formed on the wiring groove 4. As illustrated in FIG. 1C, copper is then embedded in the wiring groove 4 by electrolytic plating etc., to form a lower wiring layer 6.
Copper adhering to the surface of the interlaminar insulating layer 2, and the remaining barrier metal 5, are then removed by chemical polishing (hereinafter, “CMP”), to flatten the surface of the interlaminar insulating layer 2, and then a first low-dielectric layer 7, a first etching stopper film 8, a second low-dielectric layer 9 and a second etching stopper film 10 are laminated thereon in this order. A resist mask 11 having a pattern for forming a via hole is then formed on the second etching stopper film 10. As illustrated in FIG. 1D, the resist mask 11 is used in etching, whereby a via hole 12 penetrating the second etching stopper film 10, the second low-dielectric body 9, the first etching stopper layer 8 and the first low-dielectric layer 7 and reaching the surface of the lower wiring layer 6 is formed. As illustrated in FIG. 2E, embedded material 13 such as a photoresist material is then charged into the via hole 12. The embedded material 13 is etched back so that as illustrated in FIG. 2F, the material 13 having a desired thickness was left in the bottom of the via hole 12, and a resist mask 14 having a trench-forming pattern is formed on the second etching stopper film 10. As illustrated in 2G, the second etching stopper film 10 and the second low-dielectric layer 9 are etched using the resist mask 14, whereby a trench 15 is formed and simultaneously the embedded material 13 remaining at the bottom of the via hole 12 is removed. Thereafter, copper is embedded in the via hole 12 and the trench 15, to form a via wire 16 and upper wiring layer 17, as illustrated in FIG. 2H. A multilayer wiring structure having the lower layer wiring layer 6 connected electrically through the via wire 16 to the upper wiring layer 17 is thus realized.
In the multilayer wiring structure obtained by the process, the trench corresponds to the first etching space or the second etching space, and the via hole corresponds to the second etching space or the first etching space. In the process illustrated in FIG. 1, therefore, the dual damascene structure is constituted by the trench 15 and the via hole 12 connected to the bottom of the trench 15.
In the method of forming the dual damascene structure, an embedded material is used. The role of the embedded material is as follows. That is, upon etching for forming the trench after forming the via hole, existence of a exposed portion of the substrate at the bottom of the via hole may cause damage on the lower wiring layer on the substrate by the etching gas for forming the trench, which may result in defects in wiring. The embedded material is thus charged into the via hole to protect the lower wiring layer in the trench formation step.
As the embedded material, a photoresist composition is conventionally used. However, when such a photoresist composition is charged into the via hole, the composition may form bubbles to cause defect in embedding. It is therefore proposed to use, as a new filler material, a solution having a heat-crosslinking compound dissolved in an organic solvent. (Japanese Patent Application Laid-open No. 2002-033257)
In the constitution using the organic film as an filler material, there is however a problem that removal of the embedded material remaining in the via hole is not easy after use, thus requiring its removal by oxygen plasma ashing. In this case, the low-dielectric layer may be damaged by an ashing gas (mainly an oxygen-based gas). The damage includes a change of Si—R bond into Si—OH bond or an increase in dielectric constant (k) in the low-dielectric layer.
A photoresist is used in forming a wiring layer, and exposed to light in patterning, but there is a known problem that the exposure light is reflected by the surface of the undercoating layer, and the reflected light enters a non-light-exposed region, to reduce the patterning resolution of the resist. A technique of arranging, below the resist layer, an undercoating layer for the purpose of preventing exposure light from being reflected is known, and the undercoating layer is composed of a resin composition having a high ability to absorb the exposure light, and plays a role in preventing reflection of exposure light by absorbing patterning light for the upper resist thereby preventing the light from reaching the surface of the undercoating layer. It may be considered that the material for forming the lower anti reflective coating film can also be used as a n embedded material for forming the dual damascene structure. If the anti reflective coating film can be removed without using O2 plasma ashing, the problem in the dual damascene structure formation method can be solved.
As a material for the anti reflective coating film, various materials have been proposed. For example, a resin composition containing a polymer having an iminosulfonate group and a solvent is proposed. (Japanese Patent Application Laid-open No. H10-319601)
A light-absorbing polymer containing a polymer having a hydroxystyrene unit that has a specific substituent group containing a sulfonate has been developed, (Japanese Patent Application Laid-open No. 2000-512336) and an anti reflective coating film material including the light absorbing polymer and a solvent has been proposed. (Japanese Patent Application Laid-open No. 2000-512402)
The anti reflective coating film material disclosed in the Japanese Patent Application Laid-open No. H10-319601 uses a polymer having an iminosulfonate group as a resin component, and the resin component is insoluble in a stripping solution for photoresist. In the techniques disclosed in the Japanese Patent Application Laid-open No. H10-319601, therefore, the upper photoresist pattern is removed with the stripping solution, and then the remaining undercoating layer is removed by O2 plasma ashing.
The resin components disclosed in the Japanese Patent Application Laid-open Nos. 2000-512336 and 2000-512402 are also insoluble in the stripping solution for photoresist so that after the photoresist pattern is removed with the stripping solution, the remaining undercoating layer is removed by O2 plasma ashing.
Accordingly, even if the conventional anti reflective coating film is employed as the embedded material for forming a dual damascene structure, the problem attributable to removal of the embedded material cannot be solved.
On the other hand, use of a spin-on-glass material as the filler material for forming a dual damascene structure is conceivable. Use of the spin-on-glass material as the filler material is disclosed in for example U.S. Pat. No. 6,329,118. The spin-on-glass material can be removed with a stripping solution, and thus the remaining embedded material can be removed without using O2 plasma ashing, and the problem of deterioration in the low-dielectric layer can be eliminated.
However, a phenomenon called poisoning that often occurs upon use of the low dielectric layer as the interlaminar insulating layer for supporting the wiring layer is recently problematic in the step of forming the dual damascene structure, and this problem also occurs even upon use of the spin-on-glass material as the filler material or the filler material removable by O2 plasma ashing, and there is a need for solving it.
The above-described poisoning causes a significant defect in the shape of the second etching space 15 obtained in the wiring formation process illustrated in FIG. 2G. FIG. 3 is a schematic view showing a normal etching space and an etching space having defect in shape. FIG. 3A is an enlarged plan view of an essential part where the trench (second etching space) 15 can be formed normally without the poisoning phenomenon, and 3B is an enlarged plan view of an essential part where the poisoning phenomenon occurred to cause defects in the shape of the trench (second etching space) 15. In FIG. 3, the same element as in FIGS. 1 and 2 is given the same symbol to simplify the description. FIG. 3B is illustrated with relatively higher magnification than FIG. 3A. As illustrated in the figures, the embedded material and the photoresist layer are deteriorated by the poisoning phenomenon due to a basic substance generated from the low-dielectric layer 9, and the resist pattern is formed such that the via hole (first etching space) 12 is covered therewith, and the shape of the trench 15 is significantly deformed.
The above-described poisoning phenomenon occurs easily upon use of the low dielectric layer as the interlaminar insulating layer, and cannot be prevented by the conventional filler material for forming the dual damascene structure. Accordingly, there is demand at present for development of the filler material capable of preventing the poisoning phenomenon while maintaining a property of entering into the etching space and easiness of removal after use in the process for forming a dual damascene structure using a low-dielectric layer.